EXPLAIN PIN DIAGRAM OF 8051

Port 0(p0.0 to p0.7):
It is 8-bit bi-directional I/O port. It is bit/ byte addressable. During external memory access, it functions as multiplexed data and low-order address bus AD0-AD7.

Port 1 (p1.0 to p1.7): 
It is 8-bit bi-directional I/O port. It is bit/ byte addressable. When logic '1' is written into port latch then it works as input mode. It functions as simply I/O port and it does not have any alternative function. 

Port 2 (p2.0 to p2.7): 
It is 8-bit bi-directional I/O port. It is bit/ byte addressable. During external memory access it functions as higher order address bus (A8-A15). 

Port 3(p3.0 to port 3.7):
It is 8-bit I/O port. In an alternating function each pins can be used as a special function I/O pin. 

P3.0-RxD:
It is an Input signal. Through this I/P signal microcontroller receives serial data of serial communication circuit.

P3.1-TxD:
It is O/P signal of serial port. Through this signal data is transmitted. 

P3.2- (INT0):
It is external hardware interrupt I/P signal. Through this user, programmer or peripheral interrupts to microcontroller. 

P3.3-(INT1):
It is external hardware interrupt I/P signal. Through this user, programmer or peripheral interrupts to microcontroller.

P3.4- T0:
It is I/P signal to internal timer-0 circuit. External clock pulses can connects to timer-0 through this I/P signal.

P3.5-T1:
It is I/P signal to internal timer-1 circuit. External clock pulses can connects to timer-1 through this I/P signal.

P3.6-[WR(bar)]:
It is active low write O/P control signal. During External RAM (Data memory) access it is generated by microcontroller. when [WR(bar)]=0, then performs write operation. 

P3.7-[RD(bar)]:
It is active low read O/P control signal. During External RAM (Data memory) access it is generated by microcontroller. when [RD(bar)]=0, then performs read operation from external RAM. 

XTAL1 and XTAL2:
These are two I/P line for on-chip oscillator and clock generator circuit. A resonant network as quartz crystal is connected between these two pin. 8051 microcontroller also drives from external clock, then XTAL2 is used to drive 8051 from external clock and XTAL1 should be grounded. 

[EA(bar)]/VPP:
It is and active low I/P to 8051 microcontroller. when (EA)= 0, then 8051 microcontroller access from external program memory (ROM) only. When (EA) = 1, then it access internal and external program memories (ROMS). 

[PSEN(bar)]:
It is active low O/P signal. It is used to enable external program memory (ROM). When [PSEN(bar)]= 0, then external program memory becomes enabled and microcontroller read content of external memory location. Therefore it is connected to (OE) of external ROM. It is activated twice every external ROM memory cycle. 

ALE:
Address latch enable: It is active high O/P signal. When it goes high, external address latch becomes enabling and lower address of external memory (RAM or ROM) latched into it. Thus it separates A0-A7 address from AD0-AD7. It provides properly timed signal to latch lower byte address. The ALE is activated twice in every machine cycle. If external RAM & ROM is not accessed, then ALE is activated at constant rate of 1/6 oscillator frequency, which can be used as a clock pulses for driving external devices. 

RESET: 
It is active high I/P signal. It should be maintained high for at least two machine cycle while oscillator is running then 8051 microcontroller resets